In advanced chip packaging methods, WLCSP (Wafer Level Chip Scale Packaging) is a method in which packaging and testing is performed on the entire wafer. The wafer's surface is coated with polyimide materials, and then single IC packaging chips are singulated, thus, the package size is almost equivalent to that of the original chip. This kind of package has good heat dissipation and electrical parameters, and other good performances.
Typically, in a complex process flow of WLCSP, the most important step is to thin a chip to a certain thickness. However, the thinner the chip, the easier to be broken, which requires a packaging method to avoid any form of damage caused to the chip during its processing steps. For example, wafer cutting can easily cause cracks at edges of the chip, which consequentially causes loss of angle in the resulted unqualified chips.
An example of a conventional package currently known as FBP (Flat Bump Package), in which, the package 150 in FIG. 1J is prepared according to the Process Flow in FIGS. 1A-1J. As shown in FIG. 1A, a lead frame 100 includes a contact terminal 101 and a bonding pad 102. As shown in FIGS. 1B-1C, chip 110 is connected to the bonding pad 102 through the conductive material 103. The chip 110 is electrically connected to the contact terminal 101 through the bonding line 104, as shown in FIG. 1D.
The plastic packing is then performed as shown in FIGS. 1E-1F. The chip 110 and bonding line 104 are encapsulated within plastic packing material 120. The lead frame 100 is etched from its bottom surface to obtain the contact terminal 101 and bonding pad 102 protruding out from plastic packing material 120. Then a gold layer is coated on outer surface of contact terminal 101 and bonding pad 102 to form a gold layer 105, as shown in FIG. 1G. A film layer 130 is pasted on the top surface 120a of the package as shown in FIG. 1H. The plastic packing material 120 is cut through the lines 120c and the film layer 130 is removed, which forms a completed package 150 including chip 110 and bonding line 104 covered with plastic packing material 120 as shown in FIG. 1I-1J.
In package 150, bonding pad 102 is used for heat dissipation or used as an electrode. The contact terminal 101 and bonding pad 102 are both connected on PCB and other bases that are connected with the external circuit. Because chip 110 is bonded on the bonding pad 102 resulting on its larger size, and a certain degree of arc height is required for bonding line 104, it against the requirement of reducing the thickness of plastic packing material 120. In addition, the bonding lines, such as bonding line 104, are likely to result in the negative effects of a discrete inductance. Therefore, the size and electrical performance of package 150 in FIG. 1J is not satisfactory.
Thus, the embodiments of the invention are arrived, which is based on the following considerations: the chip is firstly packed and then thinned to make the final package have a better size and have better heat dissipation and electrical parameters and other good performances; in the packaging process, chip's angle missing risk is reduced, and the thinner chip thickness is obtained.